1. Field
Example embodiments relate to a sense amplifying circuit, and for example, to a sense amplifying circuit for a nonvolatile memory device.
2. Description of Related Art
Examples of conventional nonvolatile memory devices may be mask read only memory (ROM), electrically erasable and programmable read only memory (EEPROM), and/or erasable and programmable read only memory (EPROM). EEPROM has been widely used for system programming requiring continuous update or as an auxiliary memory device. For example, flash EEPROM (hereinafter, referred to as a flash memory device) having a higher degree of integration than normal EEPROM may be very advantageous as a large-capacity auxiliary memory device. Flash memory devices may largely be divided into NAND flash memory devices, NOR flash memory devices, and/or AND flash memory devices. NAND flash memory devices may have a higher degree of integration and may usually be used to store data. NOR flash memory devices may have a higher data access speed and may be used to store program codes.
FIG. 1 is a block diagram of a conventional NOR-type nonvolatile memory device 10, e.g., a NOR flash memory device. Referring to FIG. 1, the nonvolatile memory device 10 may include a memory cell array 15, a control circuit 20, a source line driver 25, an address buffer 30, a row decoder 35, a column decoder 40, a column gate 45, a sense amplifying circuit 50, and/or an input/output (I/O) buffer 55.
The memory cell array 15 may include a plurality of memory cells each implemented by a MOS transistor including a floating gate and/or a control gate. A drain of the MOS transistor may be connected with a bit line and/or a source thereof may be connected with a common source line. For example, when electrons are injected into the floating gate and a threshold voltage is increased, data “0” may be stored in each memory cell. When electrons escape from the floating gate and the threshold voltage is decreased, data “1” may be stored in the memory cell. A memory cell having the increased threshold voltage may be referred to as a programmed cell or an off-cell while a memory cell having the decreased threshold voltage may be referred to as an erased cell or an on-cell.
The control circuit 20 may generate an internal control signal IC corresponding to an operating mode of the nonvolatile memory device 10 based on an external control signal Co1.
The source line driver 25 may control a voltage of the common source line connected with the memory cells based on the internal control signal IC according to a desired or predetermined operating mode (e.g., a read-out mode). For example, the source line driver 25 may set a ground voltage on the common source line in the read-out mode.
The address buffer 30 may buffer an external address ADD and may output an internal address ADD′, e.g., a row address and a column address, to the row decoder 35 and/or the column decoder 40 based on the internal control signal IC.
The row decoder 35 may select a word line connected with memory cells based on the internal control signal IC and the row address.
The column decoder 40 and/or the column gate 45 may select a bit line connected with memory cells based on the internal control signal IC and/or the column address.
The sense amplifying circuit 50 may sense data of a memory cell connected with both of the selected word line and the selected bit line and/or may amplify the sensed data.
The I/O buffer 55 may buffer an output of the sense amplifying circuit 50 and/or may output a buffered signal to an I/O terminal in response to the internal control signal IC.
As nonvolatile memory devices have higher capacity and/or become thinner, the development of nonvolatile memory devices capable of operating with lower voltage has been demanded.
During a read operation in a nonvolatile memory device, it may be important to reduce a swing width of a bit line voltage of a memory cell in order to increase a read speed, secure stable current for the memory cell, and/or prevent disturbance, e.g., a data error in the memory cell. FIGS. 2 through 5 illustrate conventional sense amplifying circuits for a nonvolatile memory device.
A conventional sense amplifying circuit 200 or 300 illustrated in FIG. 2 or 3 needs a power supply voltage Vcc of at least 1.2 V in order to realize normal clamping of a bit line voltage VBL by a first transistor QN1 or QN2, which may be connected between a load transistor QP1 or QP2 of a sense amplifier 210 or 310 and a data line DL or a reference data line RDL, respectively. The data line DL may be selectively connected with a bit line BL0 and the reference data line RDL may be a signal line selectively connected with a reference bit line. For example, the sum of voltages, e.g., Vtp of 0.5 V, Vdsn of 0.2 V, and/or VBL of 0.5 V, respectively needed for the load transistor QP2, the first transistor QN2, and/or the reference data line RDL is 1.2 V, and the power supply voltage Vcc needs to be at least 1.2 V. Accordingly, the conventional sense amplifying circuit 200 or 300 may not operate with the power supply voltage Vcc of 1 V or less.
In a conventional sense amplifying circuit 400 illustrated in FIG. 4, a load transistor QP11 may serve as a load and/or serve to clamp a bit line voltage in order to decrease the power supply voltage Vcc needed to operate the sense amplifying circuit 400. For example, the power supply voltage Vcc needed to operate the conventional sense amplifying circuit 400 may be the sum of a voltage Vdsp (=0.2 V) needed for a load transistor QP12 and a voltage VBL (=0.5) needed for the reference data line RDL, i.e., Vdsp+VBL=0.7 V. Accordingly, the conventional sense amplifying circuit 400 may operate with the power supply voltage Vcc of 1 V or less.
However, because a large-capacity bit line capacitor may be directly connected with the load transistor QP11 in a higher-capacity nonvolatile memory device, the response speed of a sense terminal SA of the sense amplifying circuit 400 may be decreased and/or disturbance may occur in a memory cell MC. Time taken to read data in the nonvolatile memory device may be increased. Because the change of the power supply voltage Vcc applied to the sense amplifying circuit 400 may result in the change of the bit line voltage, stable current for a memory cell in the nonvolatile memory device may not be secured.
A conventional sense amplifying circuit 500 illustrated in FIG. 5 may operate with the power supply voltage Vcc of 1 V or less similar to the conventional sense amplifying circuit 400 illustrated in FIG. 4. In the conventional sense amplifying circuit 500 illustrated in FIG. 5, a bias voltage, which may not be affected by the change of the power supply voltage Vcc applied to the sense amplifying circuit 500, may be used as a gate signal of a load transistor QN01. Accordingly, the conventional sense amplifying circuit 500 may secure stable current for a memory cell in a nonvolatile memory device, thereby reducing disturbance in the memory cell. However, because a bit line may be charged with a voltage between a gate and a source of the load transistor QN01, transient response characteristics may be deteriorated and/or time taken to read data may be increased.
As described above, conventional sense amplifying circuits for a nonvolatile memory device may not operate with lower power supply voltage (e.g., 1 V), or if they operate, read speed may be decreased or disturbance may occur in a memory cell.